How to ensure signal integrity when the RK3588 core board has concurrent 6-channel Gigabit Ethernet?

Concurrent 6-channel Gigabit Ethernet imposes extremely high requirements on the routing between the switch chip and the PHY. In PCB design, a 10-layer or 12-layer and above stackup structure must be adopted to provide a complete reference ground plane for each set of differential lines; strictly control the impedance of differential pairs (typically 100Ω±5%) and intra-pair/inter-pair length matching; at the same time, adopt a partitioned design on the power layer to avoid digital switching noise coupling to the network transformer, ensuring that the bit error rate of high-speed data transmission meets the standards.

What are the key points of PCB power and thermal design when mounting dual RK1828 AI computing cards?

Dual M.2 AI computing cards will significantly increase the transient current demand of the motherboard. In power design, independent DC-DC step-down circuits must be configured for the M.2 slots, supplemented by low-ESR solid-state capacitors to filter out high-frequency ripples. In terms of thermal management, the computing cards should be laid out in well-ventilated board-edge areas, avoiding being adjacent to the CPU or power modules with severe heat generation; the PCB copper foil needs to be treated with large-area grounded heat dissipation, combined with the thermal silicone pads of the external metal chassis, to build a complete passive cooling system, ensuring stable operation in the -40℃~+85℃ wide-temperature environment.

What are the key routing requirements for LPDDR5 on an RK3588 core board?

LPDDR5 can run at up to 6400 Mbps, so three things matter most: length and impedance control — keep intra-byte-lane skew within ±5 mil, with 50Ω single-ended and 100Ω differential impedance; reference plane integrity — avoid crossing plane splits and place return-path ground vias next to every layer transition; and via/crosstalk control — minimize via stub length and keep at least 3W spacing between adjacent signal groups. The B2B connector between the core board and carrier board should also reserve enough GND pins for return current.

What RK3588 customization services does Qiyun Zhixun offer, and what are the lead times?

We provide one-stop RK3588 services: core board customization, carrier/base board design, high-speed SI/PI simulation, PCB fabrication and SMT assembly, plus enclosure and thermal design. Standard core board design files are typically delivered in 3-7 working days; a customized carrier board takes about 4-6 weeks from schematic to prototype, and volume delivery depends on component lead time. We support industrial (-40~85℃) and high-reliability railway/military applications.

Hardware Design and SI Analysis of RK3588 Edge Computing Board

1. Challenges Posed by the Edge AI Explosion to Embedded Hardware Design

In the fields of edge computing and robotics in 2026, Rockchip RK3588 has become a benchmark for domestic high-end embedded main controllers with its 8nm process, octa-core CPU architecture, and 6TOPS NPU computing power. Recently, Rockchip further demonstrated the "RK3588+RK1828" dual-chip heterogeneous architecture at the Apsara Conference, pushing edge AI computing power to new heights. However, the release of computing power cannot be separated from the support of underlying hardware. Taking a recently released flagship-grade RK3588 industrial development board in the industry as an example, it integrates 6-channel Gigabit Ethernet, 6-channel MIPI CSI camera interfaces, and dual M.2 AI computing card slots. This "full-interface" design poses extremely stringent requirements on PCB layout and routing, signal integrity (SI), and power integrity (PI).

As a technical team deeply engaged in PCB design and military/railway embedded systems, Xi'an Qiyun Zhixun Electronic Technology Co., Ltd. believes that in domestic substitution and high-reliability scenarios (such as railway train control, industrial vision, and military edge gateways), how to balance high computing power, multiple interfaces, and industrial-grade wide-temperature reliability is a gap that hardware engineers must cross.

2. High-Density PCB Design and Signal Integrity (SI) Considerations for the Core Board

The RK3588 chip has dense pins and supports high-speed signals such as LPDDR5, PCIe 3.0, and multiple MIPI/DP interfaces. In the core board design, adopting a castellated hole + LGA hybrid package (e.g., 426 pins) can compress the volume to 50mm×52mm, but it also greatly increases routing density and crosstalk risks.

1. Stackup Design and Impedance Control

Facing the concurrent demands of 6-channel Gigabit Ethernet and multiple high-speed cameras, the core board usually needs to adopt a 12-layer or higher high-density PCB stackup design. By setting up independent ground signal layers and complete reference planes, the impedance continuity of high-speed differential lines (such as PCIe 3.0, USB 3.0, and Gigabit Ethernet TX/RX) is ensured. The ENIG (Electroless Nickel Immersion Gold) process not only ensures soldering reliability but also effectively reduces the skin effect loss of high-frequency signals.

2. SI Optimization for LPDDR5 and B2B Connectors

The high bandwidth of LPDDR5 has extremely high requirements for length matching and timing. During the PCB design phase, it is necessary to strictly control the number of vias and the parasitic capacitance caused by layer changes, adopting blind and buried via processes to optimize signal paths. At the same time, the selection of B2B high-speed connectors between the core board and the baseboard must consider the stability of contact impedance under high-temperature (85℃) and vibration environments to avoid bit errors caused by signal reflection.

3. Industrial-Grade Multi-Interface Expansion and Electromagnetic Compatibility (EMC) Design

In industrial gateway and machine vision scenarios, the simultaneous operation of 6-channel Gigabit Ethernet ports and 6-channel MIPI CSI interfaces is highly susceptible to power noise and spatial electromagnetic interference.

1. Power Integrity (PI) and Thermal Management for Dual M.2 AI Computing Cards

Dual M.2 slots (PCIe 3.0 + PCIe 2.1) are used to mount AI computing cards such as RK1828, which means the motherboard needs to withstand additional peak power consumption. In PI design, multi-phase power supply and large-capacity solid-state capacitor arrays must be adopted to ensure that the voltage ripple under dynamic load is controlled within ±3%. In addition, the high heat generation of the computing cards requires the PCB layout to strictly follow the "heat source isolation" principle, cooperating with thermal pads and metal chassis to form an efficient passive heat dissipation path.

2. Interface Isolation and EMC Protection

For strong electromagnetic interference environments such as railways and the military, the 6-channel Gigabit Ethernet ports need to be equipped with independent network transformers and isolation circuits; industrial buses such as RS485/CAN FD must incorporate TVS diodes and optocoupler isolation designs. During PCB layout, analog signals (such as camera MIPI lines) and digital high-frequency signals must maintain a safe distance and be wrapped with ground copper to meet industrial-grade ESD Level 4 electrostatic and EMC protection standards.

4. Selection Recommendations for Domestic Substitution and High-Reliability Scenarios

In Xinchuang (IT Application Innovation) and equipment informatization projects, the "full domestication" and "long lifecycle" of hardware are core indicators. When providing customized RK3588 development services for customers, Qiyun Zhixun recommends focusing on the following dimensions:

Fully Domestic BOM Closed Loop: From the main SoC, LPDDR5/eMMC to PHY chips and power management ICs, 100% domestic brand substitution must be achieved to ensure an autonomous and controllable supply chain, meeting the audit requirements of military and railway projects.
Wide-Temperature and Reliability Verification: The industrial-grade RK3588 solution must pass -40℃~+85℃ wide-temperature tests, as well as 12 reliability verifications including 7×24-hour full-load aging and high/low-temperature cycling.
Carrier Board Reuse and Standardization: Adopting standard COMe or SMARC form factor core boards can decouple the baseboard design. Integrators only need to customize the baseboard according to the number of network ports and PCIe expansion requirements, greatly shortening the R&D cycle and reducing NRE costs.

Xi'an Qiyun Zhixun Electronic Technology Co., Ltd. focuses on high-end PCB design, FPGA development, and customized domestic embedded boards. We are committed to providing one-stop solutions from schematic design, high-speed SI/PI simulation to PCB layout and prototyping/patching for fields such as railway train control, military electronics, and industrial vision, helping to achieve safe and reliable deployment of domestic edge AI computing power.