What is the difference between Via-in-Pad and ordinary resin plugging?

Ordinary resin plugging only fills microvias with non-conductive resin, and the surface still needs to be covered with solder mask or undergo other treatments. Components cannot be directly soldered on the holes, nor can they be used as BGA fan-out contact points. In contrast, via-in-pad (electroplated copper filling) is based on resin plugging, filling the holes with solid copper pillars through an electroplating process and plating the surface flat. It not only possesses excellent insulating plugging and anti-gas leakage functions but also provides perfect electrical connections and thermal conduction channels, and can be directly used as BGA pads.

In the design of edge AI boards such as RK3588, how to balance advanced HDI costs and signal integrity?

Chips like the RK3588 have small BGA pitches, necessitating the use of Any-layer HDI processes. To balance cost and performance, it is recommended: 1. For core high-speed signals (such as DDR and PCIe), adopt electroplated copper filling via-in-pad combined with back-drilling processes to ensure impedance continuity; 2. For power and ordinary GPIO signals, staggered vias or non-filled via processes can be used to reduce costs; 3. Intervene in DFM reviews in advance during the stack-up design phase to optimize the aspect ratio, avoiding the blind pursuit of full-board any-layer interconnection which leads to decreased yield rates and out-of-control costs.

Analysis of Advanced HDI and Via-in-Pad Processes Driven by AI Computing Power

Introduction: The AI Computing Power Boom Reshapes the Underlying Logic of PCBs

According to the latest forecasts by Goldman Sachs and reports from EEFOCUS, the comprehensive average selling price of AI PCBs is surging in 2026, with the layer count of high-end AI server PCBs generally leaping to 20-30 layers or even over 70 layers. Against the backdrop of NVIDIA's new-generation architecture and the sinking of edge AI computing power, PCBs are evolving from traditional "connection boards" to the "core interconnect medium" that determines computing performance.

As a deep-tech enterprise deeply engaged in embedded board development and FPGA high-speed design, Xi'an Qiyun Zhixun Electronic Technology Co., Ltd. has profoundly realized the decisive role of advanced HDI (High-Density Interconnect) technology during the R&D of RK3588 edge AI core boards and high-reliability boards for military and railway train control systems. When the BGA pin pitch drops to 0.4mm or even 0.3mm, traditional fan-out routing has reached a dead end, making Via-in-Pad (VIP) and electroplated copper filling processes the only path to break through physical limits.

1. Breaking the 0.4mm Pitch Bottleneck: The Technological Evolution of Via-in-Pad Processes

In the layout of high-end SoCs like the RK3588 or large FPGAs, power/ground pins and high-speed signal pins are densely interwoven. If traditional vias are placed outside the pads, they will not only occupy precious routing channels but also introduce severe parasitic inductance, destroying signal integrity.

1. The Perfect Combination of Resin Plugging and Electroplated Copper Filling

Modern Ultra-HDI via-in-pad processes are not simply "plugging holes with resin," but rather employ a complex process of laser drilling -> resin plugging -> surface grinding -> electroplated copper filling. First, non-conductive resin is used to fill and grind the microvias flat. Subsequently, through special electroplating solution formulations and current density control, copper ions are directly deposited inside the holes to form solid "copper pillars."

2. The Strict Challenge of Aspect Ratio

According to the latest industry manufacturing standards, to ensure the reliability of electroplated copper filling and avoid voids inside the holes, the aspect ratio of microvias usually needs to be controlled between 0.75:1 and 1:1. This means that with a dielectric thickness of 0.1mm, the limit for laser-drilled hole diameters is approximately 0.1mm. This requires PCB designers to precisely match the thickness of the core and prepreg during stack-up design, which is also a core control point in Qiyun Zhixun's DFM (Design for Manufacturability) reviews.

2. The Dual Dividends of Signal Integrity (SI) and Thermal Management

In Qiyun Zhixun's FPGA high-speed signal integrity simulations and RK3588 video processing board designs, via-in-pad technology has demonstrated irreplaceable advantages.

1. Ultimate Signal Integrity Performance

For ultra-high-speed signals such as PCIe 4.0/5.0 and DDR5, the parasitic capacitance and inductance of vias are the culprits causing impedance discontinuity and signal reflection. Via-in-pad technology allows vias to be placed directly under BGA pads, eliminating the extra trace length and stub effects brought by traditional dog-bone routing. Combined with back-drilling processes or blind/buried via designs, the impedance fluctuation of high-speed channels can be controlled within ±5%, ensuring that the eye diagram opening meets stringent protocol standards.

2. The "Thermal Highway" for Edge AI Chips

The NPU of the RK3588 generates massive heat during full-load inference. Traditional thermal vias rely solely on the copper foil on the hole walls for heat conduction, which is highly inefficient. In contrast, via-in-pad with electroplated copper filling is equivalent to building solid "thermal copper pillars" inside the PCB, significantly reducing thermal resistance. Heat can be directly conducted from the bottom of the SoC to the inner power planes or the bottom heat dissipation layer. For space-constrained military embedded devices and fanless edge computing boxes, this is crucial to ensure the system does not throttle or crash.

3. High-Reliability HDI Design Guidelines for Military and Rail Transit Applications

In the fields of railway train control and military embedded systems, equipment often faces extreme temperature cycling (-55°C to +125°C) and mechanical vibrations. The reliability of microvias is directly related to the survival of the system.

1. Stacked Microvias vs. Staggered Microvias

Stacked Microvias: Microvias in upper and lower layers are directly aligned and stacked. The advantage lies in providing extremely high routing density to achieve full fan-out of BGAs; however, it requires extremely high lamination alignment accuracy, and thermal stress is concentrated on the same copper pillar.
Staggered Microvias: Microvias in upper and lower layers are staggered. Although they occupy a certain amount of board space, mechanical stress can be dispersed through the dielectric layers, performing better in resisting temperature cycling impacts. This is the preferred recommended solution for Qiyun Zhixun in aerospace and high-speed rail control projects.

2. Matching High-Frequency and High-Speed Materials

To support data transmission above 224Gbps and reduce high-frequency losses, substrate materials are comprehensively migrating to M7/M8/M9 grade ultra-low loss copper-clad laminates. When designing advanced HDI, the differences in the Z-axis coefficient of thermal expansion (Z-CTE) of different dielectric materials (such as Core and Prepreg) must be considered. Qiyun Zhixun recommends that in stack-up designs involving via-in-pad, special resin systems with low CTE should be prioritized to prevent barrel cracks during reflow soldering or extreme operating conditions.

Conclusion

From AI computing centers to edge intelligent terminals, PCB processes are undergoing a profound "semiconductorization" transformation. Via-in-pad and electroplated copper filling technologies are not only powerful tools for solving high-density routing but also the infrastructure for ensuring signal integrity and thermal management. Xi'an Qiyun Zhixun Electronic Technology Co., Ltd. will continue to rely on its profound experience in PCB design and embedded hardware development to provide customers with full-chain solutions ranging from chip selection and SI simulation to advanced HDI manufacturing, assisting domestic high-end equipment in moving forward steadily in the computing power era.